Then wiki is not explaining a cache miss very well. A cache miss generally refers to a requesting a line from cacheing memory (assuming that there is locality in the references, this would also be found in the processors on board N levels of cache), hard drives also experience this. Before there was read ahead of tracks, etc. One would use what was called RPS (Rotational Positiion Sensing) such that the code, would know, when the start of the track was about to pass under the head, and then could read in an entire track at one shot, by using chained CCW’s (IBM terminology for Channel Command Words, this was passed to the SIO (Start I/O instruction) as it’s parameter. Later changed to Start SubChannel in the XA/ESA series of machines.
While a branch prediction failure, can have it’s costs, there is no way around it, unless one just doesn’t code up any branches at all. That would be a program that made very few decisions! While I agree, that not predicting which way a branch is going to go, will lead to releasing some amount of data, out of the pipeline, with a subsequent fill of the pipeline, that “fill” should be coming from the on chip cache itself. Assuming locality of code. it’s always the far Jumps/Branches, that one starts to see paging happening.
Nope your example was perfect, it showed how algorithm selection, could lead to a different path, where the tick was not needed at all. With a few simple computations, the same answer could be achieved, assuming some margin of error with the divisor of the “average” amount of times between ticks. Even that margin of error could be reduced, by just keeping a running average. Which even as bad as some C/C++ compilers are, shouldn’t be that many instructions.